/*
 * @Description  : verilog code from HUIYU
 * @authorName   : HuangYuan
 * @github       : https://github.com/guoji-kk
 * @gitee        : https://gitee.com/guoji13663585559
 * @email        : 2744357198@qq.com
 * @version      : 1.0
 * @Date         : 2023-06-02 09:36:43
 * @LastEditTime : 2023-06-05 10:00:10
 */

module encrypt_47_top(
  clk, 
  button,
  led,
  uart_txd,
  dig1,
  dig2,
  segment1,
  segment2 
);

  input               clk;   
  input               button;         //control rd_en
  output              led; 
  output              uart_txd; 
  output              dig1;
  output              dig2;
  
  output reg [6:0] segment1;
  output reg [6:0] segment2; 
  

  wire                clk;
  wire                uart_en;
  wire                led;
  wire                uart_txd;
  wire                button;
  wire                count_en;
  wire  [63:0]        result;
  wire  [3:0]         out1;
  wire  [3:0]         out2;
  
  reg                 clk_out;  
  reg   [19:0]        counter;         
  reg                 dig1;
  reg                 dig2;
  
 
  assign  led = (result==0)?1:0;
  assign  rd_en = ~button;
  assign  out1 = result[7:4];
  assign  out2 = result[3:0];
     
  present_sram_top connect_1(
  .clk(clk_out),
  .clk_uart(clk),
  .start(rd_en),
  .uart_txd(uart_txd),
  .result(result)
  );

  initial begin
    dig1=0;
    dig2=0;
	 clk_out = 0;
	 counter = 0;
  end 
  
  //对小脚丫内部时钟进行1500000分频，每组加密过程为2秒
  always @(posedge clk) begin
	  if (counter == 749999) begin
		   counter <= 0;
		   clk_out <= ~clk_out;
	  end 
	  else begin
		 counter <= counter + 1;
	  end
	end
	
  
  always @( result ) begin
    case(out1)
			4'b0000: segment1 = 7'b0111111;
			4'b0001: segment1 = 7'b0000110;
			4'b0010: segment1 = 7'b1011011;
			4'b0011: segment1 = 7'b1001111;
			4'b0100: segment1 = 7'b1100110;
			4'b0101: segment1 = 7'b1101101;
			4'b0110: segment1 = 7'b1111101;
			4'b0111: segment1 = 7'b0000111;
			4'b1000: segment1 = 7'b1111111;
			4'b1001: segment1 = 7'b1101111;
			4'b1010: segment1 = 7'b1110111;
			4'b1011: segment1 = 7'b1111100;
			4'b1100: segment1 = 7'b0111001;
			4'b1101: segment1 = 7'b1011110;
			4'b1110: segment1 = 7'b1111001;
			4'b1111: segment1 = 7'b1110001;
    endcase
	 case(out2)
      4'b0000: segment2 = 7'b0111111;
      4'b0001: segment2 = 7'b0000110;
			4'b0010: segment2 = 7'b1011011;
			4'b0011: segment2 = 7'b1001111;
			4'b0100: segment2 = 7'b1100110;
			4'b0101: segment2 = 7'b1101101;
			4'b0110: segment2 = 7'b1111101;
			4'b0111: segment2 = 7'b0000111;
			4'b1000: segment2 = 7'b1111111;
			4'b1001: segment2 = 7'b1101111;
			4'b1010: segment2 = 7'b1110111;
			4'b1011: segment2 = 7'b1111100;
			4'b1100: segment2 = 7'b0111001;
			4'b1101: segment2 = 7'b1011110;
			4'b1110: segment2 = 7'b1111001;
			4'b1111: segment2 = 7'b1110001;
    endcase
  end
endmodule 
